1. Field of the Invention
This invention relates to a memory for use in a fuse system and, more particularly, to an electrically resettable, non-volatile memory utilizing variable threshold, field effect transistors as memory bits.
2. Description of the Prior Art
Prior art memories for fuse systems frequently employ magnetic cores as the memory bit storage elements. A magnetic core memory is non-volatile, in that it can retain stored information in the form of a flux field without standby power, and also is electrically resettable. Further, the flux state of the memory core may be read a limited number of times to determine the information stored in the memory. However, memory cores have the disadvantages of being large in size and requiring relatively high power driving circuitry.
A memory system utilizing voltage variable threshold field effect transistors is described in application Ser. No. 46,381 filed June 15, 1970 by J. R. Cricchi and assigned to the assignee of the present invention. In that memory system, a serial data word is advanced into a shift register and stored therein in voltage levels corresponding to positive and negative polarizing voltages. A system of write transmission gates communicates between the stages of the shift register and corresponding storage bits of the memory, and the gates are energized to transfer the information in the shift register to the storage bits of the memory. Further, a system of read transmission gates is provided for transferring the information stored in the memory to the shift register for reading purposes. The system of transmission gates and the buffer shift register limit the time period during which the large magnitude polarizing voltages, used to write information in the storage transistors, are applied to the semiconductor junctions in the system.
It is desirable to achieve the function of the memory as disclosed in the noted application, but in a system wherein the number of semiconductor junctions subjected to the high voltage polarizing voltage is reduced, thereby reducing the power handling capability of the circuits, and permitting a reduction of the number of buffer and gate elements required in that memory. The present invention is an improvement over that previously disclosed invention, substantially reducing the number of junctions subjected to the high polarizing voltages, and affording various other advantages.